MPR06T

Buy for the sensor after next.

8K 60 fps in, SLVS out — a design target, in development. MPR06T targets 6 Gsps per C-PHY lane and 9 Gbps per D-PHY lane — the D-PHY v3.0 standard-channel rate, and double MPR03K's measured D-PHY rate. At those rates, MPR06T would carry an 8K 60 fps RAW12 stream at full output, with room left over.

In development — first prototype November 2026 · completion H1 2027

Introduction

A test system is bought for years of service. The sensor it tests is replaced far sooner. That mismatch is why a line bought for one sensor generation can fall short of the next — the equipment was correct when it was bought. MPR06T is being designed to stay ahead of the sensor generations now on public roadmaps. It also moves the work upstream: CIS wafer test needs the same interface rates as module test, and SUGARS AI has not found an off-the-shelf receiver that covers wafer test at those rates. In development — scheduled to complete in the first half of 2027.

6 Gsps

C-PHY per lane, 41 Gbps across 3 lanes (design target)

9 Gbps

D-PHY per lane, 36 Gbps across 4 lanes (design target)

8K 60 fps

RAW12 stream at full output

SLVS

8b/10b out, clock embedded

Key Features

What makes MPR06T different

Where the part ends and the FPGA begins

MPR06T ends where your FPGA begins. MIPI C-PHY or D-PHY in; SLVS out, 8b/10b encoded — the format FPGA high-speed transceivers rated for the channel rate accept directly, using the transceiver's own reference clock. Connect the channels to the transceiver and the physical layer comes up, without an external deserializer or an interface board in between. What runs in the FPGA is the protocol layer, not a MIPI input stage.

The output follows the structure of the input

A C-PHY lane carries its symbol in the three differential signals formed among A, B and C — and that is what MPR06T sends. Each of A–B, B–C and C–A gets its own SLVS channel: three lanes in, nine channels out, each up to 7.6 Gbps (design target). From a D-PHY input, four data lanes map to four channels, each up to 11.4 Gbps (design target). Lane refers to the MIPI side and channel to the SLVS side.

The clock rides inside the data

Neither path sends a clock of its own. The 8b/10b encoding puts the timing into the data, so each SLVS channel carries its own timing. D-PHY's clock lane ends at MPR06T. On the board between MPR06T and the transceiver there is no clock trace to route, and none to length-match against the data.

Generation and status

The architecture carries over from MPR03K — the same analog front end, the same in-house circuits — moved to a faster process. The speed is the difference between a frame grabber that keeps up with the next generation of flagship mobile sensors and one that will have to ask the line to turn the sensor down. Package to be confirmed.

Specifications

MPR06T at a glance

Function MIPI C/D PHY → SLVS (receiver)

Input C-PHY 3 lanes (A, B, C trio per lane) · D-PHY 4 data lanes + 1 clock lane

Output SLVS, 8b/10b encoded, clock embedded — no separate clock channel

Host interface Compatible with FPGA high-speed transceivers

From C-PHY input IN 6 Gsps per lane, 41 Gbps across 3 lanes · OUT 9 data channels (A–B, B–C, C–A of each lane), up to 7.6 Gbps per channel (design target)

From D-PHY input IN 9 Gbps per lane, 36 Gbps across 4 lanes · OUT 4 data channels, up to 11.4 Gbps per channel (design target)

Analog front end Designed in-house — no third-party PHY IP

Package To be confirmed

Status In development — first prototype November 2026 · scheduled to complete in H1 2027

Applications

Where it is used

Mobile camera module test

Frame grabber

CMOS image sensor (CIS) wafer test

SoC emulation and verification systems

Open-source hardware

For further details and datasheets,
contact sugars@sugars.kr

Datasheets, evaluation boards, and engineering samples are available on request.