MPX03K

The panel should see what the phone will send.

MPX03K is the transmitter. It takes CML from the pattern generator and drives MIPI C-PHY or D-PHY into the display under test, at up to 3.5 Gsps per C-PHY lane — 24 Gbps across three lanes, at its output.

In production

Introduction

Display test runs in the opposite direction from camera test. There is no sensor to listen to; the equipment has to generate the signal itself, and the panel in the fixture has to receive it the way it will inside the finished product. That puts the burden on the generator. If the generator cannot reach the interface rate the panel expects, the panel is qualified against a signal it will not see in the product — and the defects that appear only at full rate stay invisible until the product is assembled. MPX03K shares its design base and in-house analog circuits with MPR03K, and its output stays clean for the same reason: the circuits were designed for test equipment, not for the inside of a phone.

3.5 Gsps

C-PHY per lane (24 Gbps across 3 lanes)

3.5 Gbps

D-PHY per lane (14 Gbps across 4 lanes)

At the pin

Where each MPX03K figure is stated — the device output

169

ball flip-chip CSP

Key Features

What makes MPX03K different

Signal path

MPX03K is the transmitter. CML in from the pattern generator; MIPI C-PHY (three lanes) or D-PHY (four data lanes and a clock) out to the panel. The interface the panel sees in the fixture is the interface it will see in the product.

Rates and timing

MPX03K drives C-PHY at up to 3.5 Gsps per lane — 24 Gbps across three lanes — and D-PHY at up to 3.5 Gbps per lane, 14 Gbps across four. Link timing comes from an on-chip PLL locked to an external reference clock. The PLL reaches lock with two delay stages where a conventional ring oscillator typically needs four, so the link comes up faster between units.

Stated at the device output

A transmitter figure here is stated at the device output, where our part of the path ends. What arrives at the far end depends on a board, a connector and a cable we did not design.

Design ownership and status

The MIPI PHY and the analog circuits are SUGARS AI's own — no third-party PHY IP, and no per-unit royalty on the interface. MPX03K is packaged in a 169-ball flip-chip CSP and is available now.

Specifications

MPX03K at a glance

Function CML → MIPI C/D PHY (transmitter)

Input CML

Output C-PHY 3 lanes (A, B, C trio per lane) · D-PHY 4 data lanes + 1 clock lane

C-PHY Up to 3.5 Gsps per lane (24 Gbps across 3 lanes)

D-PHY Up to 3.5 Gbps per lane (14 Gbps across 4 lanes)

Measurement basis At the device output

Clock On-chip PLL locked to an external reference clock

Package Flip-chip CSP, 169 balls

Status In production

Applications

Where it is used

Mobile OLED display test

Pattern generator

VR display test

SoC emulation and verification systems

Open-source hardware

For further details and datasheets,
contact sugars@sugars.kr

Datasheets, evaluation boards, and engineering samples are available on request.